1. Field of the Invention
The present invention relates to a semiconductor device and its fabrication method. More particularly, the present invention relates to a semiconductor device comprising multi-Vt MISFETs (Metal Insulator Semiconductor Field Effect Transistors) having different threshold voltages, and its fabrication method.
2. Description of the Related Art
In recent years, in order to achieve a semiconductor integrated circuit device that simultaneously has high performance and low power consumption, a multi-Vt process is commonly used in which MISFETs (hereinafter referred to as “MIS transistors”) that have the same conductivity type and different threshold voltages are embedded on the same chip.
On the other hand, an improvement in the scale of integration, performance and speed of semiconductor integrated circuit devices has been accompanied by a reduction in the film thickness of the gate insulating film of the MIS transistor. However, if a silicon oxide film is employed as the gate insulating film, then when the film thickness of the gate insulating film is below a predetermined value, leakage dramatically increases due to direct tunneling, resulting in an increase in current consumption of the chip.
Therefore, attention has been paid to a high-k constant insulating film made of HfO2, HfSiON or the like, which has a dielectric constant three times or more as high as that of a silicon oxide film. The high-k constant insulating film may be employed as a high gate insulating film instead of a silicon oxide film.
It is here assumed that the high-k insulating film is employed as a gate insulating film in a semiconductor device comprising multi-Vt MIS transistors. In this case, the semiconductor device is fabricated by a process similar to that when, for example, a SiON film is used as the gate insulating film. A method for fabricating the conventional semiconductor device will be hereinafter briefly described with reference to FIGS. 10A to 10D. FIGS. 10A to 10D are cross-sectional views showing major steps of the conventional semiconductor device fabricating method in an order in which the device is fabricated. Note that, in these figures, a Lvt region is a region in which a p-type MIS transistor having a relatively low threshold voltage is formed, and a Hvt region is a region in which a p-type MIS transistor having a relatively high threshold voltage is formed.
Initially, as shown in FIG. 10A, an isolation region 102 is formed in an upper portion of a silicon substrate 101. Thereby, of regions surrounded by the isolation region 102 in the silicon substrate 101, a region located in the Lvt region is an active region 101a of the Lvt region, and a region located in the Hvt region is an active region 101b of the Hvt region. Thereafter, an n-type channel region 103a having a first impurity concentration is formed in an upper portion of the active region 101a in the Lvt region, and an n-type channel region 103b having a second impurity concentration higher than the first impurity concentration is formed in an upper region of the active region 101b in the Hvt region. Thereafter, a high-k insulating film 104 and a metal film 105 are successively formed on the silicon substrate 101.
Next, as shown in FIG. 10B, a polysilicon film 111 is formed on the metal film 105.
Next, as shown in FIG. 10C, the polysilicon film 111, the metal film 105 and the high-k insulating film 104 in the Lvt region are successively subjected to patterning, thereby successively forming, on the active region 101a in the Lvt region, a gate insulating film 104a made of the high-k insulating film 104, and a gate electrode 120A made of a metal film 105a and a polysilicon film 111a. The polysilicon film 111, the metal film 105 and the high-k insulating film 104 in the Hvt region are successively subjected to patterning, thereby successively forming, on the active region 101b in the Hvt region, a gate insulating film 104b made of the high-k insulating film 104, and a gate electrode 120B made of a metal film 105b and a polysilicon film 111b. Thereafter, a shallow p-type source/drain region 107a is formed in the active region 101a, and a shallow p-type source/drain region 107b is formed in the active region 101b. 
Next, as shown in FIG. 10D, a sidewall 108a is formed on a side surface of the gate electrode 120A, and a sidewall 108b is formed on a side surface of the gate electrode 120B. Thereafter, a deep p-type source/drain region 109a is formed in the active region 101a, and a deep p-type source/drain region 109b is formed in the active region 101b. Thereafter, silicide films 110a1 and 110b1 are formed in upper portions of the deep p-type source/drain regions 109a and 109b, respectively, and silicide films 110a2 and 110b2 are formed in upper portions of the polysilicon films 101a and 101b in the gate electrodes 120A and 120B, respectively.